-
Notifications
You must be signed in to change notification settings - Fork 1.1k
/
xi2stx_chsts.h
197 lines (161 loc) · 7.02 KB
/
xi2stx_chsts.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
/******************************************************************************
* Copyright (C) 2017 - 2020 Xilinx, Inc. All rights reserved.
* Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*****************************************************************************/
/*****************************************************************************/
/**
*
* @file xi2stx_chsts.h
* @addtogroup i2stx Overview
* @{
*
* Format status related offsets & masks definitions related to the
* channel status format.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- --------------------------------------------------
* 1.0 kar 11/16/17 Initial release.
* </pre>
*
*****************************************************************************/
#ifndef XI2STX_CHSTS_H
#define XI2STX_CHSTS_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xi2stx.h"
/************************** Constant Definitions *****************************/
/**
* @name AES Status and Register Masks and Shifts.For formats/line protocols
* check the AES Standard specifications document.
* @{
*/
#define XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT (0) /**< Use of Channel Status
Block bit shift */
#define XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_MASK \
(1 << XI2S_TX_AES_STS_USE_OF_CH_STS_BLK_SHIFT) /**< Use of Channel
Status Block mask */
#define XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT (1) /**< Linear PCM
Identification bit shift */
#define XI2S_TX_AES_STS_LINEAR_PCM_ID_MASK \
(1 << XI2S_TX_AES_STS_LINEAR_PCM_ID_SHIFT) /**< Linear PCM
Identification mask */
#define XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT (2) /**< Audio signal pre-
emphasis bit shift */
#define XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_MASK \
(0x7 << XI2S_TX_AES_STS_AUDIO_SIG_PRE_EMPH_SHIFT) /**< Audio signal
pre-emphasis mask */
#define XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT (5) /**< lock indication
bit shift */
#define XI2S_TX_AES_STS_LOCK_INDICATION_MASK \
(1 << XI2S_TX_AES_STS_LOCK_INDICATION_SHIFT) /**< Lock indication mask*/
#define XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT (6) /**< Sampling Frequency 0
bit shift */
#define XI2S_TX_AES_STS_SAMPLING_FREQ_E_MASK \
(0x3 << XI2S_TX_AES_STS_SAMPLING_FREQ_E_SHIFT) /**< Sampling Frequency
0 mask */
#define XI2S_TX_AES_STS_CH_MODE_SHIFT (0) /**< Channel mode bit shift */
#define XI2S_TX_AES_STS_CH_MODE_MASK \
(0xF << XI2S_TX_AES_STS_CH_MODE_SHIFT) /**< Channel mode mask */
#define XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT (4) /**< User Bits Management
bit shift */
#define XI2S_TX_AES_STS_USR_BITS_MGMT_MASK \
(0xF << XI2S_TX_AES_STS_USR_BITS_MGMT_SHIFT) /**< User Bits
Management mask */
#define XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT (0) /**< Use of auxiliary
sample bits
bit shift */
#define XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_MASK \
(0x7 << XI2S_TX_AES_STS_USEOF_AUX_SMPL_BITS_SHIFT) /**< Use of
Auxiliary sample
bits mask */
#define XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT (3) /**< Source word
length bit shift */
#define XI2S_TX_AES_STS_SRC_WORD_LENGTH_MASK \
(0x7 << XI2S_TX_AES_STS_SRC_WORD_LENGTH_SHIFT) /**< Source word
length mask */
#define XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT (6) /**< Indication of
Alignment level
bit shift */
#define XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_MASK \
(0x3 << XI2S_TX_AES_STS_INDICATE_ALIGN_LEVEL_SHIFT) /**< Indication of
Alignment level
mask */
#define XI2S_TX_AES_STS_CH_NUM0_SHIFT (0) /**< Channel Number (0) bit shift */
#define XI2S_TX_AES_STS_CH_NUM0_MASK \
(0x7F << XI2S_TX_AES_STS_CH_NUM0_SHIFT) /**< Channel Number (0) mask */
#define XI2S_TX_AES_STS_MC_CH_MODE_SHIFT (7) /**< Multichannel mode bit shift */
#define XI2S_TX_AES_STS_MC_CH_MODE_MASK \
(1 << XI2S_TX_AES_STS_MC_CH_MODE_SHIFT) /**< Multichannel mode mask */
#define XI2S_TX_AES_STS_CH_NUM1_SHIFT (0) /**< Channel Number (1) bit shift */
#define XI2S_TX_AES_STS_CH_NUM1_MASK \
(0xF << XI2S_TX_AES_STS_CH_NUM1_SHIFT) /**< Channel Number (1) mask */
#define XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT (4) /**< Multichannel mode
number bit shift */
#define XI2S_TX_AES_STS_MC_CH_MODE_NUM_MASK \
(0x7 << XI2S_TX_AES_STS_MC_CH_MODE_NUM_SHIFT) /**< Multichannel
mode number mask */
#define XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT (0) /**< Digital Reference
Audio signal
bit shift */
#define XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_MASK \
(0x3 << XI2S_TX_AES_STS_DIGITAL_AUDIO_REF_SIG_SHIFT) /**< Digital
Reference Audio
signal mask */
#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT (2) /**< Reserved but undefined
(0) bit shift */
#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_MASK \
(1 << XI2S_TX_AES_STS_RSVD_BUT_UNDEF0_SHIFT) /**< Reserved but
undefined (0) mask */
#define XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT (3) /**< Sampling Frequency
(1) bit shift */
#define XI2S_TX_AES_STS_SAMPLING_FREQ_Q_MASK \
(0xF << XI2S_TX_AES_STS_SAMPLING_FREQ_Q_SHIFT) /**< Sampling Frequency
(1) mask */
#define XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT (7) /**< Sampling
Frequency scaling
flag bit shift */
#define XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_MASK \
(1 << XI2S_TX_AES_STS_SAMPLING_FREQ_SCALE_FLAG_SHIFT) /**< Sampling
Frequency scaling
flag mask */
#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT (0) /**< Reserved but undefined
(1) bit shift */
#define XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_MASK \
(0xFF << XI2S_TX_AES_STS_RSVD_BUT_UNDEF1_SHIFT) /**< Reserved but
undefined (1) mask */
#define XI2S_TX_AES_STS_ALPHANUM_CH_ORG_DATA_OFFSET (6) /**< Alphanumeric
channel origin data
register(s) offset */
#define XI2S_TX_AES_STS_ALPHANUM_CH_DEST_DATA_OFFSET (10) /**< Alphanumeric
channel destination
data bit shift */
#define XI2S_TX_AES_STS_LOCAL_SAMPLE_ADDRCODE_OFFSET (14) /**< Local sample
address code
register(s) offset*/
#define XI2S_TX_AES_STS_TIMEOFDAY_SAMPLE_ADDRCODE_OFFSET (18) /**< Time-of-day
sample address
code register(s)
offset */
#define XI2S_TX_AES_STS_RELIABLE_FLAGS_OFFSET (22) /**< Reliability flags
bit shift */
#define XI2S_TX_AES_STS_CRC_CHAR_OFFSET (23) /**< Cyclic redundancy
check character bit shift */
/** @} */
/**************************** Type Definitions *******************************/
/** @} */
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void XI2s_Tx_ReslveAesChStat(u8 I2stx_SrcBuf[]);
/************************** Variable Definitions *****************************/
/************************** Function Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* XI2STX_CHSTS_H */
/** @} */