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nvml.cpp
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nvml.cpp
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/*
* A trivial little dlopen()-based wrapper library for the
* NVIDIA NVML library, to allow runtime discovery of NVML on an
* arbitrary system. This is all very hackish and simple-minded, but
* it serves my immediate needs in the short term until NVIDIA provides
* a static NVML wrapper library themselves, hopefully in
* CUDA 6.5 or maybe sometime shortly after.
*
* This trivial code is made available under the "new" 3-clause BSD license,
* and/or any of the GPL licenses you prefer.
* Feel free to use the code and modify as you see fit.
*
* John E. Stone - john.stone@gmail.com
* Tanguy Pruvot - tpruvot@github
*
*/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "miner.h"
#include "nvml.h"
#include "cuda_runtime.h"
#ifdef USE_WRAPNVML
extern nvml_handle *hnvml;
extern char driver_version[32];
static uint32_t device_bus_ids[MAX_GPUS] = { 0 };
extern uint32_t device_gpu_clocks[MAX_GPUS];
extern uint32_t device_mem_clocks[MAX_GPUS];
extern uint32_t device_plimit[MAX_GPUS];
extern uint8_t device_tlimit[MAX_GPUS];
extern int8_t device_pstate[MAX_GPUS];
extern int32_t device_led[MAX_GPUS];
int32_t device_led_state[MAX_GPUS] = { 0 };
static __thread bool has_rgb_ok = false;
uint32_t clock_prev[MAX_GPUS] = { 0 };
uint32_t clock_prev_mem[MAX_GPUS] = { 0 };
uint32_t limit_prev[MAX_GPUS] = { 0 };
/*
* Wrappers to emulate dlopen() on other systems like Windows
*/
#if defined(_MSC_VER) || defined(_WIN32) || defined(_WIN64)
#include <windows.h>
static void *wrap_dlopen(const char *filename) {
HMODULE h = LoadLibrary(filename);
if (!h && opt_debug) {
applog(LOG_DEBUG, "dlopen(%d): failed to load %s",
GetLastError(), filename);
}
return (void*)h;
}
static void *wrap_dlsym(void *h, const char *sym) {
return (void *)GetProcAddress((HINSTANCE)h, sym);
}
static int wrap_dlclose(void *h) {
/* FreeLibrary returns nonzero on success */
return (!FreeLibrary((HINSTANCE)h));
}
#else
/* assume we can use dlopen itself... */
#include <dlfcn.h>
#include <errno.h>
static void *wrap_dlopen(const char *filename) {
void *h = dlopen(filename, RTLD_NOW);
if (h == NULL && opt_debug) {
applog(LOG_DEBUG, "dlopen(%d): failed to load %s",
errno, filename);
}
return (void*)h;
}
static void *wrap_dlsym(void *h, const char *sym) {
return dlsym(h, sym);
}
static int wrap_dlclose(void *h) {
return dlclose(h);
}
#endif
nvml_handle* nvml_create(){
int i=0;
#if defined(WIN32)
/* Windows (do not use slashes, else ExpandEnvironmentStrings will mix them) */
#define libnvidia_ml "%PROGRAMFILES%\\NVIDIA Corporation\\NVSMI\\nvml.dll"
#else
/* linux assumed */
#define libnvidia_ml "libnvidia-ml.so"
#endif
char tmp[512];
#ifdef WIN32
ExpandEnvironmentStrings(libnvidia_ml, tmp, sizeof(tmp));
#else
strcpy(tmp, libnvidia_ml);
#endif
void *nvml_dll = wrap_dlopen(tmp);
if (nvml_dll == NULL) {
#ifdef WIN32
nvml_dll = wrap_dlopen("nvml.dll");
if (nvml_dll == NULL)
#endif
return NULL;
}
hnvml = (nvml_handle *) calloc(1, sizeof(nvml_handle));
hnvml->nvml_dll = nvml_dll;
hnvml->nvmlInit = (nvmlReturn_t (*)(void)) wrap_dlsym(hnvml->nvml_dll, "nvmlInit_v2");
if (!hnvml->nvmlInit)
hnvml->nvmlInit = (nvmlReturn_t (*)(void)) wrap_dlsym(hnvml->nvml_dll, "nvmlInit");
hnvml->nvmlDeviceGetCount = (nvmlReturn_t (*)(int *)) wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetCount_v2");
if (!hnvml->nvmlDeviceGetCount)
hnvml->nvmlDeviceGetCount = (nvmlReturn_t (*)(int *)) wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetCount");
hnvml->nvmlDeviceGetHandleByIndex = (nvmlReturn_t (*)(int, nvmlDevice_t *))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetHandleByIndex_v2");
hnvml->nvmlDeviceGetAPIRestriction = (nvmlReturn_t (*)(nvmlDevice_t, nvmlRestrictedAPI_t, nvmlEnableState_t *))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetAPIRestriction");
hnvml->nvmlDeviceSetAPIRestriction = (nvmlReturn_t (*)(nvmlDevice_t, nvmlRestrictedAPI_t, nvmlEnableState_t))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceSetAPIRestriction");
hnvml->nvmlDeviceGetDefaultApplicationsClock = (nvmlReturn_t (*)(nvmlDevice_t, nvmlClockType_t, unsigned int *clock))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetDefaultApplicationsClock");
hnvml->nvmlDeviceGetApplicationsClock = (nvmlReturn_t (*)(nvmlDevice_t, nvmlClockType_t, unsigned int *clocks))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetApplicationsClock");
hnvml->nvmlDeviceSetApplicationsClocks = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int mem, unsigned int gpu))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceSetApplicationsClocks");
hnvml->nvmlDeviceResetApplicationsClocks = (nvmlReturn_t (*)(nvmlDevice_t))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceResetApplicationsClocks");
hnvml->nvmlDeviceGetSupportedGraphicsClocks = (nvmlReturn_t (*)(nvmlDevice_t, uint32_t mem, uint32_t *num, uint32_t *))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetSupportedGraphicsClocks");
hnvml->nvmlDeviceGetSupportedMemoryClocks = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *count, unsigned int *clocksMHz))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetSupportedMemoryClocks");
hnvml->nvmlDeviceGetClockInfo = (nvmlReturn_t (*)(nvmlDevice_t, nvmlClockType_t, unsigned int *clock))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetClockInfo");
hnvml->nvmlDeviceGetMaxClockInfo = (nvmlReturn_t (*)(nvmlDevice_t, nvmlClockType_t, unsigned int *clock))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetMaxClockInfo");
hnvml->nvmlDeviceGetPciInfo = (nvmlReturn_t (*)(nvmlDevice_t, nvmlPciInfo_t *)) wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetPciInfo_v2");
if (!hnvml->nvmlDeviceGetPciInfo)
hnvml->nvmlDeviceGetPciInfo = (nvmlReturn_t (*)(nvmlDevice_t, nvmlPciInfo_t *)) wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetPciInfo");
hnvml->nvmlDeviceGetCurrPcieLinkGeneration = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *gen))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetCurrPcieLinkGeneration");
hnvml->nvmlDeviceGetCurrPcieLinkWidth = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *width))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetCurrPcieLinkWidth");
hnvml->nvmlDeviceGetMaxPcieLinkGeneration = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *gen))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetMaxPcieLinkGeneration");
hnvml->nvmlDeviceGetMaxPcieLinkWidth = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *width))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetMaxPcieLinkWidth");
hnvml->nvmlDeviceGetPowerUsage = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetPowerUsage");
hnvml->nvmlDeviceGetPowerManagementDefaultLimit = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *limit))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetPowerManagementDefaultLimit");
hnvml->nvmlDeviceGetPowerManagementLimit = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *limit))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetPowerManagementLimit");
hnvml->nvmlDeviceGetPowerManagementLimitConstraints = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *min, unsigned int *max))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetPowerManagementLimitConstraints");
hnvml->nvmlDeviceSetPowerManagementLimit = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int limit))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceSetPowerManagementLimit");
hnvml->nvmlDeviceGetName = (nvmlReturn_t (*)(nvmlDevice_t, char *, int))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetName");
hnvml->nvmlDeviceGetTemperature = (nvmlReturn_t (*)(nvmlDevice_t, int, unsigned int *))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetTemperature");
hnvml->nvmlDeviceGetFanSpeed = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetFanSpeed");
hnvml->nvmlDeviceGetPerformanceState = (nvmlReturn_t (*)(nvmlDevice_t, int *))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetPerformanceState"); /* or nvmlDeviceGetPowerState */
hnvml->nvmlDeviceGetSerial = (nvmlReturn_t (*)(nvmlDevice_t, char *, unsigned int))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetSerial");
hnvml->nvmlDeviceGetUUID = (nvmlReturn_t (*)(nvmlDevice_t, char *, unsigned int))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetUUID");
hnvml->nvmlDeviceGetVbiosVersion = (nvmlReturn_t (*)(nvmlDevice_t, char *, unsigned int))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetVbiosVersion");
hnvml->nvmlSystemGetDriverVersion = (nvmlReturn_t (*)(char *, unsigned int))
wrap_dlsym(hnvml->nvml_dll, "nvmlSystemGetDriverVersion");
hnvml->nvmlErrorString = (char* (*)(nvmlReturn_t))
wrap_dlsym(hnvml->nvml_dll, "nvmlErrorString");
hnvml->nvmlShutdown = (nvmlReturn_t (*)())
wrap_dlsym(hnvml->nvml_dll, "nvmlShutdown");
// v331
hnvml->nvmlDeviceGetEnforcedPowerLimit = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int *limit))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetEnforcedPowerLimit");
// v340
#ifdef __linux__
hnvml->nvmlDeviceClearCpuAffinity = (nvmlReturn_t (*)(nvmlDevice_t))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceClearCpuAffinity");
hnvml->nvmlDeviceGetCpuAffinity = (nvmlReturn_t (*)(nvmlDevice_t, unsigned int sz, unsigned long *cpuSet))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetCpuAffinity");
hnvml->nvmlDeviceSetCpuAffinity = (nvmlReturn_t (*)(nvmlDevice_t))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceSetCpuAffinity");
#endif
// v346
hnvml->nvmlDeviceGetPcieThroughput = (nvmlReturn_t (*)(nvmlDevice_t, nvmlPcieUtilCounter_t, unsigned int *value))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetPcieThroughput");
// v36x (API 8 / Pascal)
hnvml->nvmlDeviceGetClock = (nvmlReturn_t (*)(nvmlDevice_t, nvmlClockType_t clockType, nvmlClockId_t clockId, unsigned int *clockMHz))
wrap_dlsym(hnvml->nvml_dll, "nvmlDeviceGetClock");
if (hnvml->nvmlInit == NULL ||
hnvml->nvmlShutdown == NULL ||
hnvml->nvmlErrorString == NULL ||
hnvml->nvmlDeviceGetCount == NULL ||
hnvml->nvmlDeviceGetHandleByIndex == NULL ||
hnvml->nvmlDeviceGetPciInfo == NULL ||
hnvml->nvmlDeviceGetName == NULL)
{
if (opt_debug)
applog(LOG_DEBUG, "Failed to obtain required NVML function pointers");
wrap_dlclose(hnvml->nvml_dll);
free(hnvml);
return NULL;
}
hnvml->nvmlInit();
if (hnvml->nvmlSystemGetDriverVersion)
hnvml->nvmlSystemGetDriverVersion(driver_version, sizeof(driver_version));
hnvml->nvmlDeviceGetCount(&hnvml->nvml_gpucount);
/* Query CUDA device count, in case it doesn't agree with NVML, since */
/* CUDA will only report GPUs with compute capability greater than 1.0 */
if (cudaGetDeviceCount(&hnvml->cuda_gpucount) != cudaSuccess) {
if (opt_debug)
applog(LOG_DEBUG, "Failed to query CUDA device count!");
wrap_dlclose(hnvml->nvml_dll);
free(hnvml);
return NULL;
}
hnvml->devs = (nvmlDevice_t *) calloc(hnvml->nvml_gpucount, sizeof(nvmlDevice_t));
hnvml->nvml_pci_domain_id = (unsigned int*) calloc(hnvml->nvml_gpucount, sizeof(unsigned int));
hnvml->nvml_pci_bus_id = (unsigned int*) calloc(hnvml->nvml_gpucount, sizeof(unsigned int));
hnvml->nvml_pci_device_id = (unsigned int*) calloc(hnvml->nvml_gpucount, sizeof(unsigned int));
hnvml->nvml_pci_subsys_id = (unsigned int*) calloc(hnvml->nvml_gpucount, sizeof(unsigned int));
hnvml->nvml_cuda_device_id = (int*) calloc(hnvml->nvml_gpucount, sizeof(int));
hnvml->cuda_nvml_device_id = (int*) calloc(hnvml->cuda_gpucount, sizeof(int));
hnvml->app_clocks = (nvmlEnableState_t*) calloc(hnvml->nvml_gpucount, sizeof(nvmlEnableState_t));
/* Obtain GPU device handles we're going to need repeatedly... */
for (i=0; i<hnvml->nvml_gpucount; i++) {
hnvml->nvmlDeviceGetHandleByIndex(i, &hnvml->devs[i]);
}
/* Query PCI info for each NVML device, and build table for mapping of */
/* CUDA device IDs to NVML device IDs and vice versa */
for (i=0; i<hnvml->nvml_gpucount; i++) {
nvmlPciInfo_t pciinfo;
hnvml->nvmlDeviceGetPciInfo(hnvml->devs[i], &pciinfo);
hnvml->nvml_pci_domain_id[i] = pciinfo.domain;
hnvml->nvml_pci_bus_id[i] = pciinfo.bus;
hnvml->nvml_pci_device_id[i] = pciinfo.device;
hnvml->nvml_pci_subsys_id[i] = pciinfo.pci_subsystem_id;
hnvml->app_clocks[i] = NVML_FEATURE_UNKNOWN;
if (hnvml->nvmlDeviceSetAPIRestriction) {
hnvml->nvmlDeviceSetAPIRestriction(hnvml->devs[i], NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS,
NVML_FEATURE_ENABLED);
/* there is only this API_SET_APPLICATION_CLOCKS on the 750 Ti (340.58) */
}
if (hnvml->nvmlDeviceGetAPIRestriction) {
hnvml->nvmlDeviceGetAPIRestriction(hnvml->devs[i], NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS,
&hnvml->app_clocks[i]);
}
}
/* build mapping of NVML device IDs to CUDA IDs */
for (i=0; i<hnvml->nvml_gpucount; i++) {
hnvml->nvml_cuda_device_id[i] = -1;
}
for (i=0; i<hnvml->cuda_gpucount; i++) {
cudaDeviceProp props;
hnvml->cuda_nvml_device_id[i] = -1;
if (cudaGetDeviceProperties(&props, i) == cudaSuccess) {
device_bus_ids[i] = props.pciBusID;
for (int j = 0; j < hnvml->nvml_gpucount; j++) {
if ((hnvml->nvml_pci_domain_id[j] == (uint32_t) props.pciDomainID) &&
(hnvml->nvml_pci_bus_id[j] == (uint32_t) props.pciBusID) &&
(hnvml->nvml_pci_device_id[j] == (uint32_t) props.pciDeviceID)) {
if (opt_debug)
applog(LOG_DEBUG, "CUDA GPU %d matches NVML GPU %d by busId %u",
i, j, (uint32_t) props.pciBusID);
hnvml->nvml_cuda_device_id[j] = i;
hnvml->cuda_nvml_device_id[i] = j;
}
}
}
}
return hnvml;
}
/* apply config clocks to an used device */
int nvml_set_clocks(int dev_id)
{
nvmlReturn_t rc;
uint32_t gpu_clk = 0, mem_clk = 0;
int n = hnvml->cuda_nvml_device_id[dev_id];
if (n < 0 || n >= hnvml->nvml_gpucount)
return -ENODEV;
if (!device_gpu_clocks[dev_id] && !device_mem_clocks[dev_id])
return 0; // nothing to do
if (hnvml->app_clocks[n] != NVML_FEATURE_ENABLED) {
applog(LOG_WARNING, "GPU #%d: NVML application clock feature is not allowed!", dev_id);
return -EPERM;
}
uint32_t mem_prev = clock_prev_mem[dev_id];
if (!mem_prev)
hnvml->nvmlDeviceGetApplicationsClock(hnvml->devs[n], NVML_CLOCK_MEM, &mem_prev);
uint32_t gpu_prev = clock_prev[dev_id];
if (!gpu_prev)
hnvml->nvmlDeviceGetApplicationsClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, &gpu_prev);
hnvml->nvmlDeviceGetDefaultApplicationsClock(hnvml->devs[n], NVML_CLOCK_MEM, &mem_clk);
rc = hnvml->nvmlDeviceGetDefaultApplicationsClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, &gpu_clk);
if (rc != NVML_SUCCESS) {
applog(LOG_WARNING, "GPU #%d: unable to query application clocks", dev_id);
return -EINVAL;
}
if (opt_debug)
applog(LOG_DEBUG, "GPU #%d: default application clocks are %u/%u", dev_id, mem_clk, gpu_clk);
// get application config values
if (device_mem_clocks[dev_id]) mem_clk = device_mem_clocks[dev_id];
if (device_gpu_clocks[dev_id]) gpu_clk = device_gpu_clocks[dev_id];
// these functions works for the 960 and the 970 (346.72+), and for the 750 Ti with driver ~361+
uint32_t nclocks = 0, mem_clocks[32] = { 0 };
hnvml->nvmlDeviceGetSupportedMemoryClocks(hnvml->devs[n], &nclocks, NULL);
nclocks = min(nclocks, 32);
if (nclocks)
hnvml->nvmlDeviceGetSupportedMemoryClocks(hnvml->devs[n], &nclocks, mem_clocks);
for (uint8_t u=0; u < nclocks; u++) {
// ordered by pstate (so highest is first memory clock - P0)
if (mem_clocks[u] <= mem_clk) {
mem_clk = mem_clocks[u];
break;
}
}
uint32_t* gpu_clocks = NULL;
nclocks = 0;
hnvml->nvmlDeviceGetSupportedGraphicsClocks(hnvml->devs[n], mem_clk, &nclocks, NULL);
if (nclocks) {
if (opt_debug)
applog(LOG_DEBUG, "GPU #%d: %u clocks found for mem %u", dev_id, nclocks, mem_clk);
gpu_clocks = (uint32_t*) calloc(1, sizeof(uint32_t) * nclocks + 4);
hnvml->nvmlDeviceGetSupportedGraphicsClocks(hnvml->devs[n], mem_clk, &nclocks, gpu_clocks);
for (uint8_t u=0; u < nclocks; u++) {
// ordered desc, so get first
if (gpu_clocks[u] <= gpu_clk) {
gpu_clk = gpu_clocks[u];
break;
}
}
free(gpu_clocks);
}
rc = hnvml->nvmlDeviceSetApplicationsClocks(hnvml->devs[n], mem_clk, gpu_clk);
if (rc == NVML_SUCCESS)
applog(LOG_INFO, "GPU #%d: application clocks set to %u/%u", dev_id, mem_clk, gpu_clk);
else {
applog(LOG_WARNING, "GPU #%d: %u/%u - %s (NVML)", dev_id, mem_clk, gpu_clk, hnvml->nvmlErrorString(rc));
return -1;
}
// store previous clocks for reset on exit (or during wait...)
clock_prev[dev_id] = gpu_prev;
clock_prev_mem[dev_id] = mem_prev;
return 1;
}
/* reset default app clocks and limits on exit */
int nvml_reset_clocks(int dev_id)
{
int ret = 0;
nvmlReturn_t rc;
uint32_t gpu_clk = 0, mem_clk = 0;
int n = hnvml->cuda_nvml_device_id[dev_id];
if (n < 0 || n >= hnvml->nvml_gpucount)
return -ENODEV;
if (clock_prev[dev_id]) {
rc = hnvml->nvmlDeviceResetApplicationsClocks(hnvml->devs[n]);
if (rc != NVML_SUCCESS) {
applog(LOG_WARNING, "GPU #%d: unable to reset application clocks", dev_id);
}
clock_prev[dev_id] = 0;
ret = 1;
}
if (limit_prev[dev_id]) {
uint32_t plimit = limit_prev[dev_id];
if (hnvml->nvmlDeviceGetPowerManagementDefaultLimit && !plimit) {
rc = hnvml->nvmlDeviceGetPowerManagementDefaultLimit(hnvml->devs[n], &plimit);
} else if (plimit) {
rc = NVML_SUCCESS;
}
if (rc == NVML_SUCCESS)
hnvml->nvmlDeviceSetPowerManagementLimit(hnvml->devs[n], plimit);
ret = 1;
}
return ret;
}
/**
* Set power state of a device (9xx)
* Code is similar as clocks one, which allow the change of the pstate
*/
int nvml_set_pstate(int dev_id)
{
nvmlReturn_t rc;
uint32_t gpu_clk = 0, mem_clk = 0;
int n = hnvml->cuda_nvml_device_id[dev_id];
if (n < 0 || n >= hnvml->nvml_gpucount)
return -ENODEV;
if (device_pstate[dev_id] < 0)
return 0;
if (hnvml->app_clocks[n] != NVML_FEATURE_ENABLED) {
applog(LOG_WARNING, "GPU #%d: NVML app. clock feature is not allowed!", dev_id);
return -EPERM;
}
hnvml->nvmlDeviceGetDefaultApplicationsClock(hnvml->devs[n], NVML_CLOCK_MEM, &mem_clk);
rc = hnvml->nvmlDeviceGetDefaultApplicationsClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, &gpu_clk);
if (rc != NVML_SUCCESS) {
applog(LOG_WARNING, "GPU #%d: unable to query application clocks", dev_id);
return -EINVAL;
}
// get application config values
if (device_mem_clocks[dev_id]) mem_clk = device_mem_clocks[dev_id];
if (device_gpu_clocks[dev_id]) gpu_clk = device_gpu_clocks[dev_id];
// these functions works for the 960 and the 970 (346.72+), and for the 750 Ti with driver ~361+
uint32_t nclocks = 0, mem_clocks[32] = { 0 };
int8_t wanted_pstate = device_pstate[dev_id];
hnvml->nvmlDeviceGetSupportedMemoryClocks(hnvml->devs[n], &nclocks, NULL);
nclocks = min(nclocks, 32);
if (nclocks)
hnvml->nvmlDeviceGetSupportedMemoryClocks(hnvml->devs[n], &nclocks, mem_clocks);
if ((uint32_t) wanted_pstate+1 > nclocks) {
applog(LOG_WARNING, "GPU #%d: only %u mem clocks available (p-states)", dev_id, nclocks);
}
for (uint8_t u=0; u < nclocks; u++) {
// ordered by pstate (so highest P0 first)
if (u == wanted_pstate) {
mem_clk = mem_clocks[u];
break;
}
}
uint32_t* gpu_clocks = NULL;
nclocks = 0;
hnvml->nvmlDeviceGetSupportedGraphicsClocks(hnvml->devs[n], mem_clk, &nclocks, NULL);
if (nclocks) {
gpu_clocks = (uint32_t*) calloc(1, sizeof(uint32_t) * nclocks + 4);
rc = hnvml->nvmlDeviceGetSupportedGraphicsClocks(hnvml->devs[n], mem_clk, &nclocks, gpu_clocks);
if (rc == NVML_SUCCESS) {
// ordered desc, get the max app clock (do not limit)
gpu_clk = gpu_clocks[0];
}
free(gpu_clocks);
}
rc = hnvml->nvmlDeviceSetApplicationsClocks(hnvml->devs[n], mem_clk, gpu_clk);
if (rc != NVML_SUCCESS) {
applog(LOG_WARNING, "GPU #%d: pstate P%d (%u/%u) %s", dev_id, (int) wanted_pstate,
mem_clk, gpu_clk, hnvml->nvmlErrorString(rc));
return -1;
}
if (!opt_quiet)
applog(LOG_INFO, "GPU #%d: app clocks set to P%d (%u/%u)", dev_id, (int) wanted_pstate, mem_clk, gpu_clk);
clock_prev[dev_id] = 1;
return 1;
}
int nvml_set_plimit(int dev_id)
{
nvmlReturn_t rc = NVML_ERROR_UNKNOWN;
uint32_t gpu_clk = 0, mem_clk = 0;
int n = hnvml->cuda_nvml_device_id[dev_id];
if (n < 0 || n >= hnvml->nvml_gpucount)
return -ENODEV;
if (!device_plimit[dev_id])
return 0; // nothing to do
if (!hnvml->nvmlDeviceSetPowerManagementLimit)
return -ENOSYS;
uint32_t plimit = device_plimit[dev_id] * 1000;
uint32_t pmin = 1000, pmax = 0, prev_limit = 0;
if (hnvml->nvmlDeviceGetPowerManagementLimitConstraints)
rc = hnvml->nvmlDeviceGetPowerManagementLimitConstraints(hnvml->devs[n], &pmin, &pmax);
if (rc != NVML_SUCCESS) {
if (!hnvml->nvmlDeviceGetPowerManagementLimit)
return -ENOSYS;
}
hnvml->nvmlDeviceGetPowerManagementLimit(hnvml->devs[n], &prev_limit);
if (!pmax) pmax = prev_limit;
plimit = min(plimit, pmax);
plimit = max(plimit, pmin);
rc = hnvml->nvmlDeviceSetPowerManagementLimit(hnvml->devs[n], plimit);
if (rc != NVML_SUCCESS) {
applog(LOG_WARNING, "GPU #%d: plimit %s", dev_id, hnvml->nvmlErrorString(rc));
return -1;
}
if (!opt_quiet) {
applog(LOG_INFO, "GPU #%d: power limit set to %uW (allowed range is %u-%u)",
dev_id, plimit/1000U, pmin/1000U, pmax/1000U);
}
limit_prev[dev_id] = prev_limit;
return 1;
}
// ccminer -D -n
#define LSTDEV_PFX " "
void nvml_print_device_info(int dev_id)
{
if (!hnvml) return;
int n = hnvml->cuda_nvml_device_id[dev_id];
if (n < 0 || n >= hnvml->nvml_gpucount)
return;
nvmlReturn_t rc;
if (hnvml->nvmlDeviceGetClock) {
uint32_t gpu_clk = 0, mem_clk = 0;
fprintf(stderr, "------- Clocks -------\n");
hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, NVML_CLOCK_ID_APP_CLOCK_DEFAULT, &gpu_clk);
rc = hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_MEM, NVML_CLOCK_ID_APP_CLOCK_DEFAULT, &mem_clk);
if (rc == NVML_SUCCESS) {
fprintf(stderr, LSTDEV_PFX "DEFAULT MEM %4u GPU %4u MHz\n", mem_clk, gpu_clk);
}
hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, NVML_CLOCK_ID_APP_CLOCK_TARGET, &gpu_clk);
rc = hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_MEM, NVML_CLOCK_ID_APP_CLOCK_TARGET, &mem_clk);
if (rc == NVML_SUCCESS) {
fprintf(stderr, LSTDEV_PFX "TARGET MEM %4u GPU %4u MHz\n", mem_clk, gpu_clk);
}
hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_GRAPHICS, NVML_CLOCK_ID_CURRENT, &gpu_clk);
rc = hnvml->nvmlDeviceGetClock(hnvml->devs[n], NVML_CLOCK_MEM, NVML_CLOCK_ID_CURRENT, &mem_clk);
if (rc == NVML_SUCCESS) {
fprintf(stderr, LSTDEV_PFX "CURRENT MEM %4u GPU %4u MHz\n", mem_clk, gpu_clk);
}
}
}
int nvml_get_gpucount(int *gpucount)
{
*gpucount = hnvml->nvml_gpucount;
return 0;
}
int cuda_get_gpucount(int *gpucount)
{
*gpucount = hnvml->cuda_gpucount;
return 0;
}
int nvml_get_gpu_name(int cudaindex, char *namebuf, int bufsize)
{
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
if (!hnvml->nvmlDeviceGetName)
return -ENOSYS;
if (hnvml->nvmlDeviceGetName(hnvml->devs[gpuindex], namebuf, bufsize) != NVML_SUCCESS)
return -1;
return 0;
}
int nvml_get_tempC(int cudaindex, unsigned int *tempC)
{
nvmlReturn_t rc;
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
if (!hnvml->nvmlDeviceGetTemperature)
return -ENOSYS;
rc = hnvml->nvmlDeviceGetTemperature(hnvml->devs[gpuindex], 0u /* NVML_TEMPERATURE_GPU */, tempC);
if (rc != NVML_SUCCESS) {
return -1;
}
return 0;
}
int nvml_get_fanpcnt(int cudaindex, unsigned int *fanpcnt)
{
nvmlReturn_t rc;
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
if (!hnvml->nvmlDeviceGetFanSpeed)
return -ENOSYS;
rc = hnvml->nvmlDeviceGetFanSpeed(hnvml->devs[gpuindex], fanpcnt);
if (rc != NVML_SUCCESS) {
return -1;
}
return 0;
}
int nvml_get_current_clocks(int cudaindex, uint32_t *graphics_clock, uint32_t *mem_clock)
{
nvmlReturn_t rc;
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount) return -1;
rc = hnvml->nvmlDeviceGetClockInfo(hnvml->devs[gpuindex], NVML_CLOCK_GRAPHICS, graphics_clock);
if (rc != NVML_SUCCESS) return -1;
rc = hnvml->nvmlDeviceGetClockInfo(hnvml->devs[gpuindex], NVML_CLOCK_MEM, mem_clock);
if (rc != NVML_SUCCESS) return -1;
return 0;
}
/* Not Supported on 750Ti 340.23 */
int nvml_get_power_usage(int cudaindex, unsigned int *milliwatts)
{
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
if (!hnvml->nvmlDeviceGetPowerUsage)
return -ENOSYS;
nvmlReturn_t res = hnvml->nvmlDeviceGetPowerUsage(hnvml->devs[gpuindex], milliwatts);
if (res != NVML_SUCCESS) {
//if (opt_debug)
// applog(LOG_DEBUG, "nvmlDeviceGetPowerUsage: %s", hnvml->nvmlErrorString(res));
return -1;
}
return 0;
}
/* Not Supported on 750Ti 340.23 */
int nvml_get_pstate(int cudaindex, int *pstate)
{
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
if (!hnvml->nvmlDeviceGetPerformanceState)
return -ENOSYS;
nvmlReturn_t res = hnvml->nvmlDeviceGetPerformanceState(hnvml->devs[gpuindex], pstate);
if (res != NVML_SUCCESS) {
//if (opt_debug)
// applog(LOG_DEBUG, "nvmlDeviceGetPerformanceState: %s", hnvml->nvmlErrorString(res));
return -1;
}
return 0;
}
int nvml_get_busid(int cudaindex, int *busid)
{
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
(*busid) = hnvml->nvml_pci_bus_id[gpuindex];
return 0;
}
int nvml_get_serial(int cudaindex, char *sn, int maxlen)
{
uint32_t subids = 0;
char uuid[NVML_DEVICE_UUID_BUFFER_SIZE];
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
nvmlReturn_t res;
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
if (hnvml->nvmlDeviceGetSerial) {
res = hnvml->nvmlDeviceGetSerial(hnvml->devs[gpuindex], sn, maxlen);
if (res == NVML_SUCCESS)
return 0;
}
if (!hnvml->nvmlDeviceGetUUID)
return -ENOSYS;
// nvmlDeviceGetUUID: GPU-f2bd642c-369f-5a14-e0b4-0d22dfe9a1fc
// use a part of uuid to generate an unique serial
// todo: check if there is vendor id is inside
memset(uuid, 0, sizeof(uuid));
res = hnvml->nvmlDeviceGetUUID(hnvml->devs[gpuindex], uuid, sizeof(uuid)-1);
if (res != NVML_SUCCESS) {
if (opt_debug)
applog(LOG_DEBUG, "nvmlDeviceGetUUID: %s", hnvml->nvmlErrorString(res));
return -1;
}
strncpy(sn, &uuid[4], min((int) strlen(uuid), maxlen));
sn[maxlen-1] = '\0';
return 0;
}
int nvml_get_bios(int cudaindex, char *desc, int maxlen)
{
uint32_t subids = 0;
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
if (!hnvml->nvmlDeviceGetVbiosVersion)
return -ENOSYS;
nvmlReturn_t res = hnvml->nvmlDeviceGetVbiosVersion(hnvml->devs[gpuindex], desc, maxlen);
if (res != NVML_SUCCESS) {
if (opt_debug)
applog(LOG_DEBUG, "nvmlDeviceGetVbiosVersion: %s", hnvml->nvmlErrorString(res));
return -1;
}
return 0;
}
int nvml_get_info(int cudaindex, uint16_t &vid, uint16_t &pid)
{
uint32_t subids = 0;
int gpuindex = hnvml->cuda_nvml_device_id[cudaindex];
if (gpuindex < 0 || gpuindex >= hnvml->nvml_gpucount)
return -ENODEV;
subids = hnvml->nvml_pci_subsys_id[gpuindex];
if (!subids) subids = hnvml->nvml_pci_device_id[gpuindex];
pid = subids >> 16;
vid = subids & 0xFFFF;
// Colorful and Inno3D
if (pid == 0) pid = hnvml->nvml_pci_device_id[gpuindex] >> 16;
return 0;
}
int nvml_destroy()
{
hnvml->nvmlShutdown();
wrap_dlclose(hnvml->nvml_dll);
free(hnvml->nvml_pci_bus_id);
free(hnvml->nvml_pci_device_id);
free(hnvml->nvml_pci_domain_id);
free(hnvml->nvml_pci_subsys_id);
free(hnvml->nvml_cuda_device_id);
free(hnvml->cuda_nvml_device_id);
free(hnvml->app_clocks);
free(hnvml->devs);
free(hnvml);
return 0;
}
// ----------------------------------------------------------------------------
/**
* nvapi alternative for windows x86 binaries
* nvml api doesn't exists as 32bit dll :///
*/
#ifdef WIN32
#include "nvapi/nvapi_ccminer.h"
static unsigned int nvapi_dev_map[MAX_GPUS] = { 0 };
static NvDisplayHandle hDisplay_a[NVAPI_MAX_PHYSICAL_GPUS * 2] = { 0 };
static NvPhysicalGpuHandle phys[NVAPI_MAX_PHYSICAL_GPUS] = { 0 };
static NvU32 nvapi_dev_cnt = 0;
extern bool nvapi_dll_loaded;
int nvapi_temperature(unsigned int devNum, unsigned int *temperature)
{
NvAPI_Status ret;
if (devNum >= nvapi_dev_cnt)
return -ENODEV;
NV_GPU_THERMAL_SETTINGS thermal;
thermal.version = NV_GPU_THERMAL_SETTINGS_VER;
ret = NvAPI_GPU_GetThermalSettings(phys[devNum], 0, &thermal);
if (ret != NVAPI_OK) {
NvAPI_ShortString string;
NvAPI_GetErrorMessage(ret, string);
if (opt_debug)
applog(LOG_DEBUG, "NVAPI NvAPI_GPU_GetThermalSettings: %s", string);
return -1;
}
(*temperature) = (unsigned int) thermal.sensor[0].currentTemp;
return 0;
}
int nvapi_fanspeed(unsigned int devNum, unsigned int *speed)
{
NvAPI_Status ret;
if (devNum >= nvapi_dev_cnt)
return -ENODEV;
NvU32 fanspeed = 0;
ret = NvAPI_GPU_GetTachReading(phys[devNum], &fanspeed);
if (ret != NVAPI_OK) {
NvAPI_ShortString string;
NvAPI_GetErrorMessage(ret, string);
if (opt_debug)
applog(LOG_DEBUG, "NVAPI NvAPI_GPU_GetTachReading: %s", string);
return -1;
}
(*speed) = (unsigned int) fanspeed;
return 0;
}
int nvapi_getpstate(unsigned int devNum, unsigned int *pstate)
{
NvAPI_Status ret;
if (devNum >= nvapi_dev_cnt)
return -ENODEV;
NV_GPU_PERF_PSTATE_ID CurrentPstate = NVAPI_GPU_PERF_PSTATE_UNDEFINED; /* 16 */
ret = NvAPI_GPU_GetCurrentPstate(phys[devNum], &CurrentPstate);
if (ret != NVAPI_OK) {
NvAPI_ShortString string;
NvAPI_GetErrorMessage(ret, string);
if (opt_debug)
applog(LOG_DEBUG, "NVAPI NvAPI_GPU_GetCurrentPstate: %s", string);
return -1;
}
else {
// get pstate for the moment... often 0 = P0
(*pstate) = (unsigned int)CurrentPstate;
}
return 0;
}
#define UTIL_DOMAIN_GPU 0
int nvapi_getusage(unsigned int devNum, unsigned int *pct)
{
NvAPI_Status ret;
if (devNum >= nvapi_dev_cnt)
return -ENODEV;
NV_GPU_DYNAMIC_PSTATES_INFO_EX info;
info.version = NV_GPU_DYNAMIC_PSTATES_INFO_EX_VER;
ret = NvAPI_GPU_GetDynamicPstatesInfoEx(phys[devNum], &info);
if (ret != NVAPI_OK) {
NvAPI_ShortString string;
NvAPI_GetErrorMessage(ret, string);
if (opt_debug)
applog(LOG_DEBUG, "NVAPI GetDynamicPstatesInfoEx: %s", string);
return -1;
}
else {
if (info.utilization[UTIL_DOMAIN_GPU].bIsPresent)
(*pct) = info.utilization[UTIL_DOMAIN_GPU].percentage;
}
return 0;
}
int nvapi_getinfo(unsigned int devNum, uint16_t &vid, uint16_t &pid)
{
NvAPI_Status ret;
NvU32 pDeviceId, pSubSystemId, pRevisionId, pExtDeviceId;
if (devNum >= nvapi_dev_cnt)
return -ENODEV;
ret = NvAPI_GPU_GetPCIIdentifiers(phys[devNum], &pDeviceId, &pSubSystemId, &pRevisionId, &pExtDeviceId);
if (ret != NVAPI_OK) {
NvAPI_ShortString string;
NvAPI_GetErrorMessage(ret, string);
if (opt_debug)
applog(LOG_DEBUG, "NVAPI GetPCIIdentifiers: %s", string);
return -1;
}
pid = pDeviceId >> 16;
vid = pDeviceId & 0xFFFF;
if (vid == 0x10DE && pSubSystemId) {
vid = pSubSystemId & 0xFFFF;
pid = pSubSystemId >> 16;
// Colorful and Inno3D
if (pid == 0) pid = pDeviceId >> 16;
}
return 0;
}
int nvapi_getserial(unsigned int devNum, char *serial, unsigned int maxlen)
{
NvAPI_Status ret;
if (devNum >= nvapi_dev_cnt)
return -ENODEV;
memset(serial, 0, maxlen);
if (maxlen < 11)
return -EINVAL;
NvAPI_ShortString ser = { 0 };
ret = NvAPI_DLL_GetSerialNumber(phys[devNum], ser);
if (ret != NVAPI_OK) {
NvAPI_ShortString string;
NvAPI_GetErrorMessage(ret, string);
if (opt_debug)
applog(LOG_DEBUG, "NVAPI GetSerialNumber: %s", string);
return -1;
}
uint8_t *bytes = (uint8_t*) ser;
for (int n=0; n<5; n++) sprintf(&serial[n*2], "%02X", bytes[n]);
return 0;
}
int nvapi_getbios(unsigned int devNum, char *desc, unsigned int maxlen)
{
NvAPI_Status ret;
if (devNum >= nvapi_dev_cnt)
return -ENODEV;
if (maxlen < 64) // Short String
return -1;
ret = NvAPI_GPU_GetVbiosVersionString(phys[devNum], desc);
if (ret != NVAPI_OK) {
NvAPI_ShortString string;
NvAPI_GetErrorMessage(ret, string);
if (opt_debug)
applog(LOG_DEBUG, "NVAPI GetVbiosVersionString: %s", string);
return -1;
}
return 0;
}
static int SetAsusRGBLogo(unsigned int devNum, uint32_t RGB, bool ignorePrevState)
{
NvAPI_Status ret = NVAPI_OK;
NV_I2C_INFO_EX* i2cInfo;
int delay1 = 20000;
int delay2 = 0;
uchar4 rgb = { 0 };
memcpy(&rgb, &RGB, 4);
uchar4 prgb = { 0 };
int32_t prev = device_led_state[nvapi_devid(devNum)];
memcpy(&prgb, &prev, 4);
NV_INIT_STRUCT_ALLOC(NV_I2C_INFO_EX, i2cInfo);
if (i2cInfo == NULL) return -ENOMEM;
NvU32 data[5] = { 0 };
NvU32 datv[2] = { 0, 1 };
NvU32 datw[2] = { 1, 0 };
if (rgb.z != prgb.z || ignorePrevState) {
data[2] = 4; // R:4 G:5 B:6, Mode = 7 (1 static, 2 breath, 3 blink, 4 demo)
data[3] = 1;