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Verilog Emitter: randomize registers by default #2366

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ekiwi opened this issue Sep 23, 2021 · 0 comments

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ekiwi commented Sep 23, 2021

Jack and I talked about this on Gitter. We think that randomization should be opt-out instead of opt-in.

ekiwi added this to the 1.5.0 milestone

ekiwi assigned jackkoenig

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