defining mtval informative and unconditional writes

[neelgala]

According to the Spec mtval is a WARL field. However, a platform has a luxury to completely specify which exceptions must set mtval informatively and which may unconditionally set it to zero. To capture this the following is proposed:

1. Extend CSR template with a platform field:
   We add a boolean field platform to each csr which indicates if the platform-yaml
   has more information on the same node. The platform yaml should also contain a node with the same csr-name. The node in the isa-yaml will define the set of all legal/illegal values that mtval can take

2. Adding mtval node in platform-yaml:
   the mtval field in the platform yaml could be :

mtval:
  implemented: True
  behaviour:
    - [0, [0x00000000:0xFFFFFFFF] , "Address that was misaligned"]
    - [2, [0x00000000, 0x0000FFFF] , "lower 16-bits of Instruction that was illegal"]

Each entry under behaviour is a 3 element tuple. The first element is cause value, the second defines the set of legal values and the last element is the description.
Cause values missing in the behavior list are assumed to write "0" to mtval by default.

[stnolting]

Is this still up-to-date? 🤔

I am trying to constrain the behavior of mtval. This is my entry in *_platform.yaml:

mtval_condition_writes:
  implemented: true
  behaviour:
    - [0, [0x00000000:0xFFFFFFFF], "Instruction fetch - address that was misaligned"]
    - [1, [0x00000000:0xFFFFFFFF], "Instruction fetch - address that triggered a bus exception"]
    - [4, [0x00000000:0xFFFFFFFF], "Load access - address that was misaligned"]
    - [5, [0x00000000:0xFFFFFFFF], "Load access - address that triggered a bus exception"]
    - [6, [0x00000000:0xFFFFFFFF], "Store access - address that was misaligned"]
    - [7, [0x00000000:0xFFFFFFFF], "Store access - address that triggered a bus exception"]

But I'm getting an error here:

   ERROR |  mtval_condition_writes:
   ERROR |   behaviour:must be of dict type

What exactly is a "dict type"? The only thing I could find is https://riscv-config.readthedocs.io/en/stable/yaml-specs.html?highlight=dictionary#mtval-condition-writes but I don't really understand the documentation there 😅
I would be happy for any kind of help :)

[pawks]

I believe this has not been implemented yet. A temporary way of using this for now would be do something like the following

mtval_condition_writes:
  implemented: true
  behaviour:
    e0: "[0x00000000:0xFFFFFFFF], 'Instruction fetch - address that was misaligned']"
    e1: "[0x00000000:0xFFFFFFFF], 'Instruction fetch - address that triggered a bus exception']"
    ....

[stnolting]

I believe this has not been implemented yet.

I already thought so. Anyway, thanks for the fast response!

I have tested your code. Unfortunately, my framework version does not seem to recognize the exception code fields:

   ERROR |  mtval_condition_writes:
   ERROR |   behaviour:
   ERROR |     e0:unknown field
   ERROR |     e1:unknown field

My framework versions:

    INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.23.4 *******
    INFO | using riscv_isac version : 0.10.1
    INFO | using riscv_config version : 2.13.0

Might this be caused by a version issue?

[pawks]

Looks like the exception numbers should be double digit(link). Replacing e0 with e00 and so on fixed it. Its not a version issue.

[stnolting]

Thanks for the hint! The syntax errors are resolved now. 👍

---

However, I cannot modify the model's mtval update behavior so that it matches the DUT's one. I am still quite new to RISCOF and I do not understand all of it's internal mechanisms yet...

I have experimented with mtval_update, but without success. The next thing I have tried was to override the CODE_REL_TVAL_MSK and DATA_REL_TVAL_MSK masks from riscv-test-suite/env/arch_test.h, but this does not work either as these masks just define mtval adjustment values.

Some questions:

• All the configurations from the YAML files are not actually passed to the model - they just configure the code from riscv-arch-test, right?
• Right now, I am using Sail as reference model. Maybe Spike would support all those mtval-related YAML options?! 🤔

---

Anyway, I made a simple patch for my riscv-arch-test submodule to clear the mtval part of the signature when encountering an ebreak exception. It's not a clean solution, but I can live with it for now. 😉

[pawks]

Some questions:

* All the configurations from the YAML files are not _actually passed_ to the model - they just configure the code from `riscv-arch-test`, right?

* Right now, I am using Sail as reference model. Maybe Spike would support all those `mtval`-related YAML options?! thinking

While we do have support to specify the behaviors in the yaml, no model exists yet which can be configured directly from these specifications. Work is underway for SAIL to support all possible options as allowed by the spec. You might have more success by looking at the spike CLI options to see if any switches exist there which allow you to modify the mtval update behavior and then add those switches to the command in the riscof-plugin based on the input yaml.