|
Warning
|
This is an older proposal for a future extension after v1.0 and might change substantially or be dropped completely. Do not use this for development or production work. |
The quad-widening integer multiply-add instructions add a SEW-bit*SEW-bit multiply result to (from) a 4*SEW-bit value and produce a 4*SEW-bit result. All combinations of signed and unsigned multiply operands are supported.
|
Note
|
These instructions are currently not planned to be part of the base V extension. |
|
Note
|
On ELEN=32 machines, only 8b * 8b = 16b products accumulated in a 32b accumulator would be supported. Machines with ELEN=64 would also add 16b * 16b = 32b products accumulated in 64b. |
# Quad-widening unsigned-integer multiply-add, overwrite addend vqmaccu.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vqmaccu.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Quad-widening signed-integer multiply-add, overwrite addend vqmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] vqmacc.vx vd, rs1, vs2, vm # vd[i] = +(x[rs1] * vs2[i]) + vd[i] # Quad-widening signed-unsigned-integer multiply-add, overwrite addend vqmaccsu.vv vd, vs1, vs2, vm # vd[i] = +(signed(vs1[i]) * unsigned(vs2[i])) + vd[i] vqmaccsu.vx vd, rs1, vs2, vm # vd[i] = +(signed(x[rs1]) * unsigned(vs2[i])) + vd[i] # Quad-widening unsigned-signed-integer multiply-add, overwrite addend vqmaccus.vx vd, rs1, vs2, vm # vd[i] = +(unsigned(x[rs1]) * signed(vs2[i])) + vd[i]