LaCrosse mode 1 optimization register settings #1022
Merged
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What is the current behavior?
(You can also link to an open issue here, if this describes the current behavior)
GDO0 is defined as an output.
Interrupt is only given in the FIFOTHR register specified number of bytes triggered (can only be set in steps of 4 bytes).
16/16 + carrier-sense above threshold
What is the new behavior (if this is a feature change)?
GDO0 output pin configuration, High impedance (3-state) - unused in FSK-modes
CC1101 will wake up with optimal ADC settings for low data rate (≤ 100 kbps)
The interrupt is triggered when the number of bytes required by the message is reached.
SYNC_MODE 16/16 sync word bits detected
Does this PR introduce a breaking change? (What changes might users need to make in their application due to this PR?)
no
Other information: