Risc-V Arch

[chuckb]

I created a little example to experiment with C3 and Risc-V. I noticed that I get a WARNING! This architecture is not supported. message when I build with --target=elf-riscv32. I do get a binary and I can get it to run on qemu. I looked in the C3 compiler source code and it seems like Intel, ARM, and WASM are checked and then everything else gets this message. Is that just because you are not actively testing for the other arch(s) even though, of course, llvm will happily target them?

Also, I'd be happy to jam in my example to your list of examples and do a PR if you'd find it useful.

[lerno]

The reason it prints that, even though I've done the work on the RISC-V ABI (which is the big thing for supporting an architecture, as LLVM will provide the rest), I haven't had access to any hardware even for just doing remote CI.

It's not possible to say that a target is supported if you haven't even seen a hello world running!

So if you have a working environment, I'd be happy to work with you to ensure great support for the architecture.

[chuckb]

Got it. PR inbound. I'd be open to working on further examples/coding help to better support the arch.