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[RISCV][CFI] CFIFixup update tests
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@dlav-sc
dlav-sc committed Oct 2, 2024
1 parent aa47ba2 commit 3a74327
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Showing 9 changed files with 74 additions and 0 deletions.
1 change: 1 addition & 0 deletions llvm/test/CodeGen/RISCV/O0-pipeline.ll
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Expand Up @@ -68,6 +68,7 @@
; CHECK-NEXT: StackMap Liveness Analysis
; CHECK-NEXT: Live DEBUG_VALUE analysis
; CHECK-NEXT: Machine Sanitizer Binary Metadata
; CHECK-NEXT: Insert CFI remember/restore state instructions
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/RISCV/O3-pipeline.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -196,6 +196,7 @@
; CHECK-NEXT: Machine Sanitizer Binary Metadata
; CHECK-NEXT: Machine Outliner
; CHECK-NEXT: FunctionPass Manager
; CHECK-NEXT: Insert CFI remember/restore state instructions
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/branch-relaxation.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -2789,6 +2789,7 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-RV32-NEXT: .cfi_offset s9, -44
; CHECK-RV32-NEXT: .cfi_offset s10, -48
; CHECK-RV32-NEXT: .cfi_offset s11, -52
; CHECK-RV32-NEXT: .cfi_remember_state
; CHECK-RV32-NEXT: #APP
; CHECK-RV32-NEXT: li ra, 1
; CHECK-RV32-NEXT: #NO_APP
Expand Down Expand Up @@ -3006,6 +3007,7 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV32-NEXT: ret
; CHECK-RV32-NEXT: .LBB6_5: # %cond_3
; CHECK-RV32-NEXT: .cfi_restore_state
; CHECK-RV32-NEXT: beq t1, t2, .LBB6_4
; CHECK-RV32-NEXT: # %bb.6: # %space
; CHECK-RV32-NEXT: #APP
Expand Down Expand Up @@ -3045,6 +3047,7 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-RV64-NEXT: .cfi_offset s9, -88
; CHECK-RV64-NEXT: .cfi_offset s10, -96
; CHECK-RV64-NEXT: .cfi_offset s11, -104
; CHECK-RV64-NEXT: .cfi_remember_state
; CHECK-RV64-NEXT: #APP
; CHECK-RV64-NEXT: li ra, 1
; CHECK-RV64-NEXT: #NO_APP
Expand Down Expand Up @@ -3267,6 +3270,7 @@ define void @relax_jal_spill_32_restore_block_correspondence() {
; CHECK-RV64-NEXT: .cfi_def_cfa_offset 0
; CHECK-RV64-NEXT: ret
; CHECK-RV64-NEXT: .LBB6_5: # %cond_3
; CHECK-RV64-NEXT: .cfi_restore_state
; CHECK-RV64-NEXT: sext.w t5, t2
; CHECK-RV64-NEXT: sext.w t6, t1
; CHECK-RV64-NEXT: beq t6, t5, .LBB6_4
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/exception-pointer-register.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,7 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
; RV32I-NEXT: .cfi_remember_state
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: beqz a0, .LBB0_2
; RV32I-NEXT: # %bb.1: # %bb2
Expand All @@ -47,6 +48,7 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; RV32I-NEXT: .cfi_def_cfa_offset 0
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_4: # %lpad
; RV32I-NEXT: .cfi_restore_state
; RV32I-NEXT: .Ltmp4:
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
Expand All @@ -64,6 +66,7 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
; RV64I-NEXT: .cfi_remember_state
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: beqz a0, .LBB0_2
; RV64I-NEXT: # %bb.1: # %bb2
Expand All @@ -88,6 +91,7 @@ define void @caller(ptr %p) personality ptr @__gxx_personality_v0 {
; RV64I-NEXT: .cfi_def_cfa_offset 0
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_4: # %lpad
; RV64I-NEXT: .cfi_restore_state
; RV64I-NEXT: .Ltmp4:
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
Expand Down
8 changes: 8 additions & 0 deletions llvm/test/CodeGen/RISCV/lpad.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -144,6 +144,7 @@ define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: .cfi_remember_state
; RV32-NEXT: .Ltmp0:
; RV32-NEXT: jalr a0
; RV32-NEXT: .Ltmp1:
Expand All @@ -154,6 +155,7 @@ define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
; RV32-NEXT: .cfi_def_cfa_offset 0
; RV32-NEXT: ret
; RV32-NEXT: .LBB2_2: # %lpad
; RV32-NEXT: .cfi_restore_state
; RV32-NEXT: .Ltmp2:
; RV32-NEXT: j .LBB2_1
;
Expand All @@ -164,6 +166,7 @@ define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: .cfi_remember_state
; RV64-NEXT: .Ltmp0:
; RV64-NEXT: jalr a0
; RV64-NEXT: .Ltmp1:
Expand All @@ -174,6 +177,7 @@ define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
; RV64-NEXT: .cfi_def_cfa_offset 0
; RV64-NEXT: ret
; RV64-NEXT: .LBB2_2: # %lpad
; RV64-NEXT: .cfi_restore_state
; RV64-NEXT: .Ltmp2:
; RV64-NEXT: j .LBB2_1
;
Expand All @@ -184,6 +188,7 @@ define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
; FIXED-ONE-RV32-NEXT: .cfi_def_cfa_offset 16
; FIXED-ONE-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; FIXED-ONE-RV32-NEXT: .cfi_offset ra, -4
; FIXED-ONE-RV32-NEXT: .cfi_remember_state
; FIXED-ONE-RV32-NEXT: .Ltmp0:
; FIXED-ONE-RV32-NEXT: lui t2, 1
; FIXED-ONE-RV32-NEXT: jalr a0
Expand All @@ -195,6 +200,7 @@ define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
; FIXED-ONE-RV32-NEXT: .cfi_def_cfa_offset 0
; FIXED-ONE-RV32-NEXT: ret
; FIXED-ONE-RV32-NEXT: .LBB2_2: # %lpad
; FIXED-ONE-RV32-NEXT: .cfi_restore_state
; FIXED-ONE-RV32-NEXT: .Ltmp2:
; FIXED-ONE-RV32-NEXT: j .LBB2_1
;
Expand All @@ -205,6 +211,7 @@ define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
; FIXED-ONE-RV64-NEXT: .cfi_def_cfa_offset 16
; FIXED-ONE-RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; FIXED-ONE-RV64-NEXT: .cfi_offset ra, -8
; FIXED-ONE-RV64-NEXT: .cfi_remember_state
; FIXED-ONE-RV64-NEXT: .Ltmp0:
; FIXED-ONE-RV64-NEXT: lui t2, 1
; FIXED-ONE-RV64-NEXT: jalr a0
Expand All @@ -216,6 +223,7 @@ define void @invoke(ptr %f) personality ptr @__gxx_personality_v0 {
; FIXED-ONE-RV64-NEXT: .cfi_def_cfa_offset 0
; FIXED-ONE-RV64-NEXT: ret
; FIXED-ONE-RV64-NEXT: .LBB2_2: # %lpad
; FIXED-ONE-RV64-NEXT: .cfi_restore_state
; FIXED-ONE-RV64-NEXT: .Ltmp2:
; FIXED-ONE-RV64-NEXT: j .LBB2_1
entry:
Expand Down
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: addi s0, sp, 32
; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: .cfi_remember_state
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: li a0, 0
Expand Down Expand Up @@ -60,6 +61,7 @@ define signext i32 @foo() #1 personality ptr @__gxx_personality_v0 {
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_4: # %ehcleanup
; CHECK-NEXT: .cfi_restore_state
; CHECK-NEXT: call _Unwind_Resume
entry:
invoke void @_Z3fooiiiiiiiiiiPi(i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 signext poison, i32 poison, i32 poison, i32 poison)
Expand Down
26 changes: 26 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3156,6 +3156,7 @@ define void @mscatter_v8i64(<8 x i64> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a1, 56(a0)
; RV32ZVE32F-NEXT: lw a2, 60(a0)
; RV32ZVE32F-NEXT: lw a5, 40(a0)
Expand Down Expand Up @@ -3212,6 +3213,7 @@ define void @mscatter_v8i64(<8 x i64> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB41_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw s1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
Expand Down Expand Up @@ -3280,6 +3282,7 @@ define void @mscatter_v8i64(<8 x i64> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
; RV64ZVE32F-NEXT: .cfi_offset s0, -8
; RV64ZVE32F-NEXT: .cfi_offset s1, -16
; RV64ZVE32F-NEXT: .cfi_offset s2, -24
; RV64ZVE32F-NEXT: .cfi_remember_state
; RV64ZVE32F-NEXT: ld a4, 40(a1)
; RV64ZVE32F-NEXT: ld a3, 48(a1)
; RV64ZVE32F-NEXT: ld a2, 56(a1)
Expand Down Expand Up @@ -3332,6 +3335,7 @@ define void @mscatter_v8i64(<8 x i64> %val, <8 x ptr> %ptrs, <8 x i1> %m) {
; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB41_10: # %cond.store
; RV64ZVE32F-NEXT: .cfi_restore_state
; RV64ZVE32F-NEXT: ld a1, 0(a1)
; RV64ZVE32F-NEXT: ld a0, 0(a0)
; RV64ZVE32F-NEXT: sd a0, 0(a1)
Expand Down Expand Up @@ -3394,6 +3398,7 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -3455,6 +3460,7 @@ define void @mscatter_baseidx_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8> %id
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB42_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -3642,6 +3648,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -3703,6 +3710,7 @@ define void @mscatter_baseidx_sext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB43_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -3892,6 +3900,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -3953,6 +3962,7 @@ define void @mscatter_baseidx_zext_v8i8_v8i64(<8 x i64> %val, ptr %base, <8 x i8
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB44_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -4149,6 +4159,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -4210,6 +4221,7 @@ define void @mscatter_baseidx_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i16> %
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB45_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -4398,6 +4410,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -4459,6 +4472,7 @@ define void @mscatter_baseidx_sext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB46_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -4649,6 +4663,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -4710,6 +4725,7 @@ define void @mscatter_baseidx_zext_v8i16_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB47_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -4908,6 +4924,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -4968,6 +4985,7 @@ define void @mscatter_baseidx_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i32> %
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB48_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -5155,6 +5173,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -5215,6 +5234,7 @@ define void @mscatter_baseidx_sext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB49_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -5403,6 +5423,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_offset s0, -4
; RV32ZVE32F-NEXT: .cfi_offset s1, -8
; RV32ZVE32F-NEXT: .cfi_offset s2, -12
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a2, 56(a0)
; RV32ZVE32F-NEXT: lw a3, 60(a0)
; RV32ZVE32F-NEXT: lw a6, 40(a0)
Expand Down Expand Up @@ -5463,6 +5484,7 @@ define void @mscatter_baseidx_zext_v8i32_v8i64(<8 x i64> %val, ptr %base, <8 x i
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB50_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -5671,6 +5693,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
; RV32ZVE32F-NEXT: .cfi_offset s6, -28
; RV32ZVE32F-NEXT: .cfi_offset s7, -32
; RV32ZVE32F-NEXT: .cfi_offset s8, -36
; RV32ZVE32F-NEXT: .cfi_remember_state
; RV32ZVE32F-NEXT: lw a3, 56(a0)
; RV32ZVE32F-NEXT: lw a4, 60(a0)
; RV32ZVE32F-NEXT: lw a7, 40(a0)
Expand Down Expand Up @@ -5759,6 +5782,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
; RV32ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV32ZVE32F-NEXT: ret
; RV32ZVE32F-NEXT: .LBB51_10: # %cond.store
; RV32ZVE32F-NEXT: .cfi_restore_state
; RV32ZVE32F-NEXT: lw a1, 4(a0)
; RV32ZVE32F-NEXT: lw a0, 0(a0)
; RV32ZVE32F-NEXT: vmv.x.s s2, v8
Expand Down Expand Up @@ -5828,6 +5852,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
; RV64ZVE32F-NEXT: .cfi_offset s1, -16
; RV64ZVE32F-NEXT: .cfi_offset s2, -24
; RV64ZVE32F-NEXT: .cfi_offset s3, -32
; RV64ZVE32F-NEXT: .cfi_remember_state
; RV64ZVE32F-NEXT: ld a5, 40(a0)
; RV64ZVE32F-NEXT: ld a4, 48(a0)
; RV64ZVE32F-NEXT: ld a3, 56(a0)
Expand Down Expand Up @@ -5884,6 +5909,7 @@ define void @mscatter_baseidx_v8i64(<8 x i64> %val, ptr %base, <8 x i64> %idxs,
; RV64ZVE32F-NEXT: .cfi_def_cfa_offset 0
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB51_10: # %cond.store
; RV64ZVE32F-NEXT: .cfi_restore_state
; RV64ZVE32F-NEXT: ld a2, 0(a2)
; RV64ZVE32F-NEXT: ld a0, 0(a0)
; RV64ZVE32F-NEXT: slli a2, a2, 3
Expand Down
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