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Move from #[inline(always)] to #[inline] #306

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Jan 29, 2018
Merged

Move from #[inline(always)] to #[inline] #306

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05a0df3
Move from #[inline(always)] to #[inline]
alexcrichton Jan 29, 2018
e923961
Add inline(always) on eflags intrinsics
alexcrichton Jan 29, 2018
2ee6948
Leave #[inline(always)] on portable types
alexcrichton Jan 29, 2018
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8 changes: 4 additions & 4 deletions coresimd/src/aarch64/neon.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -8,31 +8,31 @@ use simd_llvm::simd_add;
use v128::f64x2;

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fadd))]
pub unsafe fn vadd_f64(a: f64, b: f64) -> f64 {
a + b
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fadd))]
pub unsafe fn vaddq_f64(a: f64x2, b: f64x2) -> f64x2 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 {
a + b
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 {
Expand Down
10 changes: 5 additions & 5 deletions coresimd/src/aarch64/v8.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -9,14 +9,14 @@
use stdsimd_test::assert_instr;

/// Reverse the order of the bytes.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(rev))]
pub unsafe fn _rev_u64(x: u64) -> u64 {
x.swap_bytes() as u64
}

/// Count Leading Zeros.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(clz))]
pub unsafe fn _clz_u64(x: u64) -> u64 {
x.leading_zeros() as u64
Expand All @@ -29,7 +29,7 @@ extern "C" {
}

/// Reverse the bit order.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(rbit))]
pub unsafe fn _rbit_u64(x: u64) -> u64 {
rbit_u64(x as i64) as u64
Expand All @@ -39,7 +39,7 @@ pub unsafe fn _rbit_u64(x: u64) -> u64 {
///
/// When all bits of the operand are set it returns the size of the operand in
/// bits.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(cls))]
pub unsafe fn _cls_u32(x: u32) -> u32 {
u32::leading_zeros((((((x as i32) >> 31) as u32) ^ x) << 1) | 1) as u32
Expand All @@ -49,7 +49,7 @@ pub unsafe fn _cls_u32(x: u32) -> u32 {
///
/// When all bits of the operand are set it returns the size of the operand in
/// bits.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(cls))]
pub unsafe fn _cls_u64(x: u64) -> u64 {
u64::leading_zeros((((((x as i64) >> 63) as u64) ^ x) << 1) | 1) as u64
Expand Down
46 changes: 23 additions & 23 deletions coresimd/src/arm/neon.rs
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Expand Up @@ -9,135 +9,135 @@ use v64::{f32x2, i16x4, i32x2, i8x8, u16x4, u32x2, u8x8};
use v128::{f32x4, i16x8, i32x4, i64x2, i8x16, u16x8, u32x4, u64x2, u8x16};

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vadd_s8(a: i8x8, b: i8x8) -> i8x8 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddq_s8(a: i8x16, b: i8x16) -> i8x16 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vadd_s16(a: i16x4, b: i16x4) -> i16x4 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddq_s16(a: i16x8, b: i16x8) -> i16x8 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vadd_s32(a: i32x2, b: i32x2) -> i32x2 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddq_s32(a: i32x4, b: i32x4) -> i32x4 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddq_s64(a: i64x2, b: i64x2) -> i64x2 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vadd_u8(a: u8x8, b: u8x8) -> u8x8 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddq_u8(a: u8x16, b: u8x16) -> u8x16 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vadd_u16(a: u16x4, b: u16x4) -> u16x4 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddq_u16(a: u16x8, b: u16x8) -> u16x8 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vadd_u32(a: u32x2, b: u32x2) -> u32x2 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddq_u32(a: u32x4, b: u32x4) -> u32x4 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(add))]
pub unsafe fn vaddq_u64(a: u64x2, b: u64x2) -> u64x2 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fadd))]
pub unsafe fn vadd_f32(a: f32x2, b: f32x2) -> f32x2 {
simd_add(a, b)
}

/// Vector add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fadd))]
pub unsafe fn vaddq_f32(a: f32x4, b: f32x4) -> f32x4 {
simd_add(a, b)
}

/// Vector long add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(saddl))]
pub unsafe fn vaddl_s8(a: i8x8, b: i8x8) -> i16x8 {
Expand All @@ -147,7 +147,7 @@ pub unsafe fn vaddl_s8(a: i8x8, b: i8x8) -> i16x8 {
}

/// Vector long add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(saddl))]
pub unsafe fn vaddl_s16(a: i16x4, b: i16x4) -> i32x4 {
Expand All @@ -157,7 +157,7 @@ pub unsafe fn vaddl_s16(a: i16x4, b: i16x4) -> i32x4 {
}

/// Vector long add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(saddl))]
pub unsafe fn vaddl_s32(a: i32x2, b: i32x2) -> i64x2 {
Expand All @@ -167,7 +167,7 @@ pub unsafe fn vaddl_s32(a: i32x2, b: i32x2) -> i64x2 {
}

/// Vector long add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uaddl))]
pub unsafe fn vaddl_u8(a: u8x8, b: u8x8) -> u16x8 {
Expand All @@ -177,7 +177,7 @@ pub unsafe fn vaddl_u8(a: u8x8, b: u8x8) -> u16x8 {
}

/// Vector long add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uaddl))]
pub unsafe fn vaddl_u16(a: u16x4, b: u16x4) -> u32x4 {
Expand All @@ -187,7 +187,7 @@ pub unsafe fn vaddl_u16(a: u16x4, b: u16x4) -> u32x4 {
}

/// Vector long add.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(uaddl))]
pub unsafe fn vaddl_u32(a: u32x2, b: u32x2) -> u64x2 {
Expand All @@ -205,7 +205,7 @@ extern "C" {
}

/// Reciprocal square-root estimate.
#[inline(always)]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(frsqrte))]
pub unsafe fn vrsqrte_f32(a: f32x2) -> f32x2 {
Expand Down
4 changes: 2 additions & 2 deletions coresimd/src/arm/v6.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -10,14 +10,14 @@
use stdsimd_test::assert_instr;

/// Reverse the order of the bytes.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(rev))]
pub unsafe fn _rev_u16(x: u16) -> u16 {
x.swap_bytes() as u16
}

/// Reverse the order of the bytes.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(rev))]
pub unsafe fn _rev_u32(x: u32) -> u32 {
x.swap_bytes() as u32
Expand Down
8 changes: 4 additions & 4 deletions coresimd/src/arm/v7.rs
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Expand Up @@ -13,28 +13,28 @@ pub use super::v6::*;
use stdsimd_test::assert_instr;

/// Count Leading Zeros.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(clz))]
pub unsafe fn _clz_u8(x: u8) -> u8 {
x.leading_zeros() as u8
}

/// Count Leading Zeros.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(clz))]
pub unsafe fn _clz_u16(x: u16) -> u16 {
x.leading_zeros() as u16
}

/// Count Leading Zeros.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(clz))]
pub unsafe fn _clz_u32(x: u32) -> u32 {
x.leading_zeros() as u32
}

/// Reverse the bit order.
#[inline(always)]
#[inline]
#[cfg_attr(test, assert_instr(rbit))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg(dont_compile_me)] // FIXME need to add `v7` upstream in rustc
Expand Down
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