testbenches

Here are 23 public repositories matching this topic...

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

nxbyte / Verilog-Projects

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This repository contains source code for past labs and projects involving FPGA and Verilog based designs

simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder

Updated Oct 2, 2019
Verilog

snbk001 / Verilog-Design-Examples

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Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous F…

verilog testbenches verilog-hdl verilog-programs verilog-project verilog-code verilog-design self-checking

Updated Jan 29, 2024
Verilog

BrianHGinc / BrianHG-DDR3-Controller

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DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

fpga intel verilog xilinx altera systemverilog lattice hdl testbenches ddr3

Updated Apr 8, 2024
SystemVerilog

tmeissner / cryptocores

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cryptography ip-cores in vhdl / verilog

cryptography fpga vhdl verilog testbenches ghdl

Updated Feb 20, 2021
VHDL

mihir8181 / VerilogHDL-Codes

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Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

Updated May 10, 2019
Verilog

tmeissner / libvhdl

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Library of reusable VHDL components

coverage fpga vhdl verification assertions testbenches ghdl formal-verification osvvm psl

Updated Mar 7, 2024
VHDL

Crimsonninja / senior_design_puf

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Repository to store all design and testbench files for Senior Design

rtl verilog systemverilog hardware-designs testbenches xilinx-vivado hardware-security physical-unclonable-functions ring-oscillator

Updated Apr 16, 2020
Verilog

TILhub / AMBA-3-AHB-Lite-Protocol

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This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol

arm cplusplus protocol emulation stl systemc lite testbenches testbench amba ahb-lite

Updated Jul 11, 2018
C++

gabrielebaris / iir-audio-filter-fpga

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Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA

fpga matlab filter vhdl vivado testbenches digital-systems iir-filters

Updated Mar 29, 2018
VHDL

geddy11 / netwiz

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Network protocol libraries for VHDL test benches

Updated Jun 22, 2024
VHDL

ste7en / Project-Reti-Logiche-Testbench-Generator

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A "C pseudorandom generator" of VHDL testbenches for Digital Systems Design project at Politecnico di Milano.

c vhdl testbenches testbench

Updated Jan 27, 2019
C

Saadia-Hassan / Types-of-Verification-Using-SRAM

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This repo contains golden vector and randomization testbenches for SRAM module.

sram testbenches verification-methodologies verilog-hdl verilog-project vlsi-design

Updated Aug 2, 2020
Verilog

kuby1412 / Open-Source-Verilog-Projects

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This repository contains source code for labs and projects involving FPGA and Verilog based designs

fpga verilog testbenches xilinx-vivado

Updated Sep 20, 2020
Verilog

AlPrime2k1 / Sequential-Logic-Circuits

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Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

testbenches verilog-hdl digital-design verilog-code

Updated May 21, 2023
Verilog

Shehab-Naga / VHDL-Exercises

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My work for the laboratory exercises provided by intel FPGAcademy (Digital Logic) during my internship at PyramidTech in Summer 2022.

fpga vhdl testbenches quartus digital-logic-design-lab

Updated Sep 17, 2022
VHDL

HarinandanAM / FPGA

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This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. Each project includes HDL code, testbenches, simulations, and pin assignments, providing a comprehensive view of the FPGA design process.