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This repository contains systemverilog codes for the purpose of learning modeling and design verification.

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Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
basic		basic
clk_gen		clk_gen
README.md		README.md
common.mk		common.mk

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SystemVerilog_examples

This repository contains Systemverilog codes for the purpose of learning modeling and design verification.

To build and execute any example:

Go to the example directory. eg: basic
Type "make run"

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This repository contains systemverilog codes for the purpose of learning modeling and design verification.

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